Digital Design
RTL, FPGA, verification, and physical-design oriented work across architecture and implementation.
About
I'm Mark Sui, an Electrical and Computer Engineering student at the University of California, San Diego, currently pursuing a Master of Science in Electrical and Computer Engineering. I already hold Bachelor of Science degrees in Computer Engineering and Mathematics.
My work sits around hardware, software, and applied mathematics. I am especially interested in hardware, SoC performance, computer architecture, RTL design, and VLSI-related engineering roles.
Open to hardware-focused software, RTL, and VLSI-adjacent engineering work.
Start with the projects that best show my hardware-minded tool building and practical systems work.
Core Skills
Architecture
Computer architecture, datapath design, throughput analysis, and performance-aware hardware thinking.
AI Systems
Evaluation pipelines, regression analysis, robustness testing, and Python tooling around model behavior.
Math + Embedded
Applied mathematics, algorithms, and embedded system integration from sensing to board-level work.
Featured Projects
Featured
Logic & CMOS Studio
Browser-based tool that turns Boolean logic into truth tables, K-maps, simplified equations, Verilog, and static CMOS pull-up / pull-down schematics.
Featured
Hardware Interview Trainer
Local-first interview practice app with a 160-question bank, timed mock rounds, wrong-question review, progress analytics, and JSON import / export.
Featured
MarkMacZip
Local archive app for macOS that compresses and extracts common formats, supports password workflows, tracks job history, and keeps files on device.
Selected Highlights
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Current Education Focus
UC San Diego / Electrical and Computer Engineering
Recent coursework and project focus include Digital IC Design (VLSI), Computer Architecture, FPGA / RTL Design, timing analysis, and hardware verification. -
Research Fellow - Handshake AI Fellowship
Jun 2025 - Dec 2025 / Remote
Built Python-based evaluation pipelines for agentic LLM systems, designed robustness stress tests, and analyzed 10,000+ execution traces to identify regressions and failure modes. -
Recent Portfolio Projects
Educational EDA, interview preparation, and local-first macOS software
Built Logic & CMOS Studio, Hardware Interview Trainer, and MarkMacZip as polished public projects around hardware learning, tool-building, and practical desktop utility. -
Technical Skills
Architecture, hardware design, performance, and tools
Verilog/SystemVerilog, RTL design and verification, FPGA, Quartus, ModelSim, Cadence Virtuoso, Innovus, SRAM-based memory systems, C/C++, Python, JavaScript, Git, Linux, TCL, and MATLAB.