Mark Sui - RTL Design Engineer Portfolio

ASIC / FPGA / Software Engineering

UCSD · Math · CE · ECE.

I'm Mark Sui. My background combines UC San Diego ECE, computer engineering, and applied mathematics. I work from cycle-level RTL and FPGA implementation to software tools that make complex systems easier to build and verify.

Seeking ASIC / FPGA / Software Engineering roles.

Explore Dual-Core Accelerator Resume PDF Contact

More Engineering Work

Direct RTL Evidence Digital Design / SystemVerilog / FPGA

SystemVerilog Viterbi Decoder

Designed a convolutional encoder and modular Viterbi decoder with branch-metric, add-compare-select, and traceback units aligned cycle by cycle.

Architecture: Decomposed the decoder into BMC, ACS, and Traceback modules.
Built With: SystemVerilog, FPGA-oriented RTL, simulation, waveform debugging.
Verification: Recorded 22 error-injection cases; zero output errors in periodic cases 2a1–2a5.

Architecture & results Source code

Logic and CMOS Studio interface showing the Boolean formula workspace and gate-level circuit diagram

Public Design Tool Logic + CMOS / Verilog / React

Logic & CMOS Studio

Browser-based tool connecting Boolean expressions to truth tables, K-maps, simplified logic, generated Verilog, and static CMOS schematics.

Role: Designed and built the end-to-end logic exploration workflow.
Built With: React, TypeScript, Boolean logic, Verilog, static CMOS.
Why It Matters: Makes the transformation from logic specification to implementation inspectable.

Live app Source

Report-Backed RTL Research VerilogEval / Python / RTL Debugging

MAGE RTL Generation

Extended a multi-agent Verilog generation flow with failure routing, route-specific repair prompts, edit guards, and task-local debugging memory.

Problem: Generated RTL can compile yet still fail from interface, timing, or behavioral mismatches.
Built With: Python, VerilogEval-V2, Icarus Verilog, routed repair workflows.
Evidence: Public source and a report documenting the routing and memory experiments.

Report PDF Source

Skills

01 / DESIGN

RTL & Digital Hardware

Verilog · SystemVerilog · MAC datapaths · SRAM interfaces · asynchronous FIFOs

Dual-core architecture →

02 / VERIFY

Simulation & Debugging

Testbenches · waveform analysis · reference comparisons · error injection

Viterbi verification →

03 / IMPLEMENT

Implementation & Tools

Synthesis · place & route · timing / power / area analysis · Python experiment tooling

Implementation tradeoffs →

Experience

Jul — Aug 2026 Data Quality Reviewer AfterQuery Jun 2025 — Jun 2026 Research Fellow Handshake Jun — Dec 2024 Embedded Systems Intern Shandong Haike

View complete experience →