Mark Sui - About

About

ECE, hardware, and the personal archive around it.

I’m Mark Sui, an Electrical and Computer Engineering student at the University of California, San Diego, currently pursuing a Master of Science in Electrical and Computer Engineering. I already hold Bachelor of Science degrees in Computer Engineering and Mathematics.

My work sits around hardware, software, and applied mathematics. I am especially interested in hardware, SoC performance, computer architecture, RTL design, and VLSI-related engineering roles.

Technical Work Academic Path Travel Archive Get in Touch

Core Skills

Digital Design

RTL, FPGA, verification, and physical-design oriented work across architecture and implementation.

Verilog SystemVerilog FPGA Timing

Architecture

Computer architecture, datapath design, throughput analysis, and performance-aware hardware thinking.

ISA Pipelines CDC SRAM

AI Systems

Evaluation pipelines, regression analysis, robustness testing, and Python tooling around model behavior.

Python PyTorch Tracing QA

Math + Embedded

Applied mathematics, algorithms, and embedded system integration from sensing to board-level work.

Analysis Algorithms ESP32 PCB

Recent Project Builds

Educational EDA Tool · React / TypeScript

Logic & CMOS Studio

Browser-based tool that turns Boolean logic into truth tables, K-maps, simplified equations, Verilog, and static CMOS pull-up / pull-down schematics.

Live app Source

Hardware Prep Tool · React / TypeScript

Hardware Interview Trainer

Local-first interview practice app with a 160-question bank, timed mock rounds, wrong-question review, progress analytics, and JSON import / export.

Live app Source

macOS Utility · Swift / C++

MarkMacZip

Local archive app for macOS that compresses and extracts common formats, supports password workflows, tracks job history, and keeps files on device.

Project page Source Releases

Selected Highlights

Current Education Focus
UC San Diego · Electrical and Computer Engineering
Recent coursework and project focus include Digital IC Design (VLSI), Computer Architecture, FPGA / RTL Design, timing analysis, and hardware verification.
Research Fellow – Handshake AI Fellowship
Jun 2025 – Dec 2025 · Remote
Built Python-based evaluation pipelines for agentic LLM systems, designed robustness stress tests, and analyzed 10,000+ execution traces to identify regressions and failure modes.
Recent Portfolio Projects
Educational EDA, interview preparation, and local-first macOS software
Built Logic & CMOS Studio, Hardware Interview Trainer, and MarkMacZip as polished public projects around hardware learning, tool-building, and practical desktop utility.
Technical Skills
Architecture, hardware design, performance, and tools
Verilog/SystemVerilog, RTL design and verification, FPGA, Quartus, ModelSim, Cadence Virtuoso, Innovus, SRAM-based memory systems, C/C++, Python, JavaScript, Git, Linux, TCL, and MATLAB.

Skills

Programming

Python C C++ Java JavaScript MATLAB TCL Verilog SystemVerilog

Hardware & Architecture

Computer Architecture RTL Design RTL Verification FPGA ASIC / VLSI CMOS Logic VHDL SRAM Memory Systems

Performance & Verification

Timing Closure Pipeline Balancing CDC Optimization Throughput / Latency VCD Waveforms Regression Testing

AI & Data Science

Machine Learning Deep Learning PyTorch TensorFlow NumPy Pandas Data Analysis Computer Graphics

Embedded Systems

ESP32 Arduino PCB Design I2C SPI UART Sensor Integration

Math & Algorithms

Cryptography Numerical Analysis Real Analysis Applied Mathematics Linear Algebra Probability Algorithms Data Structures Graph Algorithms

Tools

Git Linux LaTeX Jupyter Quartus ModelSim Cadence Virtuoso Innovus

Productivity & Design

Word Excel PowerPoint Access Photoshop Illustrator

Languages

Mandarin Chinese English Japanese (Basic)