Clear datapaths, control logic, and cycle-level behavior.
Breaking complex designs into traceable modules with explicit interfaces, state, and timing relationships.
RTL Design Engineer / Digital Hardware
Designing reliable RTL from microarchitecture through verification and implementation.
I'm Mark Sui, an Electrical and Computer Engineering master's student at UC San Diego. My work centers on SystemVerilog RTL, FPGA design, digital microarchitecture, verification, and the VLSI implementation flow around them.
Seeking RTL design and digital design roles where cycle-level correctness, clear module boundaries, verification, and implementation trade-offs matter.
Target Role
RTL Design
HDL
SystemVerilog / Verilog
Design Flow
Simulation / FPGA
Implementation
VLSI / Physical Design
Open to RTL design, digital design, and FPGA engineering opportunities.
Start with the Viterbi decoder for direct RTL evidence, then review the public tools and report-backed work.
RTL Design Focus
Designs that can be tested, explained, and repaired.
Using controlled cases, simulation results, and waveform reasoning to isolate behavioral and timing errors.
RTL decisions informed by the downstream VLSI flow.
Connecting front-end design choices to synthesis, timing, power, area, and physical-design constraints.
Technical Map
Digital Design
RTL, FPGA, verification, and physical-design oriented work across architecture and implementation.
Architecture
Computer architecture, datapath design, throughput analysis, and performance-aware hardware thinking.
AI Systems
Evaluation pipelines, regression analysis, robustness testing, and Python tooling around model behavior.
Math + Embedded
Applied mathematics, algorithms, and embedded system integration from sensing to board-level work.
Selected RTL Projects
Direct RTL Evidence
FPGA-Based Viterbi Decoder
Designed a convolutional encoder and modular Viterbi decoder with branch-metric, add-compare-select, and traceback units aligned cycle by cycle.
- Architecture
- Decomposed the decoder into BMC, ACS, and Traceback modules.
- Built With
- SystemVerilog, FPGA-oriented RTL, simulation, waveform debugging.
- Verification
- Used controlled error cases to keep path metrics and traceback behavior traceable.
Public Design Tool
Logic & CMOS Studio
Browser-based tool connecting Boolean expressions to truth tables, K-maps, simplified logic, generated Verilog, and static CMOS schematics.
- Role
- Designed and built the end-to-end logic exploration workflow.
- Built With
- React, TypeScript, Boolean logic, Verilog, static CMOS.
- Why It Matters
- Makes the transformation from logic specification to implementation inspectable.
Report-Backed RTL Research
MAGE RTL Generation
Extended a multi-agent Verilog generation flow with failure routing, route-specific repair prompts, edit guards, and task-local debugging memory.
- Problem
- Generated RTL can compile yet still fail from interface, timing, or behavioral mismatches.
- Built With
- Python, VerilogEval-V2, Icarus Verilog, routed repair workflows.
- Evidence
- Public source and a report documenting the routing and memory experiments.
Selected Highlights
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Current Education Focus
UC San Diego / Electrical and Computer Engineering
Recent coursework and project focus include Digital IC Design (VLSI), Computer Architecture, FPGA / RTL Design, timing analysis, and hardware verification. -
Research Fellow - Handshake AI Fellowship
Jun 2025 - Jun 2026 / Remote
Built Python-based evaluation pipelines for agentic LLM systems, designed robustness stress tests, and analyzed 10,000+ execution traces to identify regressions and failure modes. -
Data Quality Reviewer - AfterQuery
Jul 2026 - Aug 2026 / Remote
Reviewed and verified 8,000+ structured data fields using English- and Chinese-language sources, with field-level checks for exact values, evidence quality, consistency, and traceable review notes. -
Quarter Project Reports
RTL generation, CUDA cryptography, MBFF clustering, and OpenROAD physical design
Added report-backed case studies from this quarter, including VerilogEval/MAGE work, GPU GGM tree construction, and ECE 260C physical-design optimization projects. -
Technical Skills
Architecture, hardware design, performance, and tools
Verilog/SystemVerilog, RTL design and verification, FPGA, Quartus, ModelSim, Cadence Virtuoso, Innovus, SRAM-based memory systems, C/C++, Python, JavaScript, Git, Linux, TCL, and MATLAB.