Logic interfaces that preserve engineering traceability.
Turning Boolean expressions into connected views: truth tables, K-maps, Verilog, and CMOS-level reasoning.
ECE Portfolio / Hardware-minded Software
RTL, VLSI, embedded systems, and tools that make hardware ideas easier to inspect.
I'm Mark Sui, an Electrical and Computer Engineering master's student at UC San Diego with Computer Engineering and Mathematics foundations. I build at the boundary between digital hardware, systems, and practical engineering interfaces.
Best fit: teams working on RTL design, VLSI workflows, computer architecture, embedded sensing, or developer tools where correctness, usability, and traceability all matter.
Current
UC San Diego ECE
Hardware Signal
RTL / VLSI
Tool Stack
React / Python / C++
Foundation
CE + Mathematics
Open to hardware-focused software, RTL, VLSI-adjacent engineering, embedded systems, and systems tooling work.
Start with the project spotlight for the fastest read on my strongest engineering signal.
Now Building
Preparation tools with repeatable feedback loops.
Structured question banks, timed practice, missed-topic review, and local progress for hardware interviews.
Local-first tools for practical workflows.
Focused desktop utilities for archives, documents, coursework, and privacy-sensitive everyday work.
Technical Map
Digital Design
RTL, FPGA, verification, and physical-design oriented work across architecture and implementation.
Architecture
Computer architecture, datapath design, throughput analysis, and performance-aware hardware thinking.
AI Systems
Evaluation pipelines, regression analysis, robustness testing, and Python tooling around model behavior.
Math + Embedded
Applied mathematics, algorithms, and embedded system integration from sensing to board-level work.
Featured Projects
Featured
Logic & CMOS Studio
Browser-based tool that turns Boolean logic into truth tables, K-maps, simplified equations, Verilog, and static CMOS pull-up / pull-down schematics.
- Role
- Designed and built the browser workflow end to end.
- Built With
- React, TypeScript, Boolean logic, Verilog, static CMOS.
- Why It Matters
- Connects course abstractions instead of leaving each view in a separate tool.
Featured
Hardware Interview Trainer
Local-first interview practice app with a 160-question bank, timed mock rounds, wrong-question review, progress analytics, and JSON import / export.
- Role
- Built the practice flow, progress model, and review interface.
- Built With
- React, TypeScript, local storage, structured question data.
- Why It Matters
- Makes hardware prep measurable, repeatable, and portable.
Featured
MarkMacZip
Local archive app for macOS that compresses and extracts common formats, supports password workflows, tracks job history, and keeps files on device.
- Role
- Shaped the native utility workflow and release-facing project page.
- Built With
- Swift, C++, macOS file handling, local archive workflows.
- Why It Matters
- Turns a frequent file task into a private, focused desktop tool.
Selected Highlights
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Current Education Focus
UC San Diego / Electrical and Computer Engineering
Recent coursework and project focus include Digital IC Design (VLSI), Computer Architecture, FPGA / RTL Design, timing analysis, and hardware verification. -
Research Fellow - Handshake AI Fellowship
Jun 2025 - Dec 2025 / Remote
Built Python-based evaluation pipelines for agentic LLM systems, designed robustness stress tests, and analyzed 10,000+ execution traces to identify regressions and failure modes. -
Recent Portfolio Projects
Educational EDA, interview preparation, and local-first macOS software
Built Logic & CMOS Studio, Hardware Interview Trainer, and MarkMacZip as polished public projects around hardware learning, tool-building, and practical desktop utility. -
Quarter Project Reports
RTL generation, CUDA cryptography, MBFF clustering, and OpenROAD physical design
Added report-backed case studies from this quarter, including VerilogEval/MAGE work, GPU GGM tree construction, and ECE 260C physical-design optimization projects. -
Technical Skills
Architecture, hardware design, performance, and tools
Verilog/SystemVerilog, RTL design and verification, FPGA, Quartus, ModelSim, Cadence Virtuoso, Innovus, SRAM-based memory systems, C/C++, Python, JavaScript, Git, Linux, TCL, and MATLAB.