Mark Sui - RTL Design Engineer Portfolio

ASIC / FPGA / Software Engineering

UCSD · Math · CE · ECE.

UCSD
MATH
CE
ECE

I'm Mark Sui, an ECE master's student at UC San Diego with a mathematics and computer engineering foundation. I work from cycle-level RTL and FPGA implementation to software tools that make complex systems easier to build and verify.

Seeking ASIC / FPGA / Software Engineering roles.

Explore Viterbi Decoder Resume PDF Contact

Target Role ASIC / FPGA / SWE

HDL SystemVerilog / Verilog

Design Flow Simulation / FPGA

Implementation Hardware / Software

RTL Signal Flow

01 / SPECIFICATION Start with behavior that can be stated cycle by cycle. Interfaces · latency · constraints

Selected RTL Projects

Direct RTL Evidence Digital Design / SystemVerilog / FPGA

SystemVerilog Viterbi Decoder

Designed a convolutional encoder and modular Viterbi decoder with branch-metric, add-compare-select, and traceback units aligned cycle by cycle.

Architecture: Decomposed the decoder into BMC, ACS, and Traceback modules.
Built With: SystemVerilog, FPGA-oriented RTL, simulation, waveform debugging.
Verification: Recorded 22 error-injection cases; zero output errors in periodic cases 2a1–2a5.

Architecture & results Source code

Logic and CMOS Studio interface showing the Boolean formula workspace and gate-level circuit diagram

Public Design Tool Logic + CMOS / Verilog / React

Logic & CMOS Studio

Browser-based tool connecting Boolean expressions to truth tables, K-maps, simplified logic, generated Verilog, and static CMOS schematics.

Role: Designed and built the end-to-end logic exploration workflow.
Built With: React, TypeScript, Boolean logic, Verilog, static CMOS.
Why It Matters: Makes the transformation from logic specification to implementation inspectable.

Live app Source

Report-Backed RTL Research VerilogEval / Python / RTL Debugging

MAGE RTL Generation

Extended a multi-agent Verilog generation flow with failure routing, route-specific repair prompts, edit guards, and task-local debugging memory.

Problem: Generated RTL can compile yet still fail from interface, timing, or behavioral mismatches.
Built With: Python, VerilogEval-V2, Icarus Verilog, routed repair workflows.
Evidence: Public source and a report documenting the routing and memory experiments.

Report PDF Source

Experience

Jul — Aug 2026 Data Quality Reviewer AfterQuery Jun 2025 — Jun 2026 Research Fellow Handshake Jun — Dec 2024 Embedded Systems Intern Shandong Haike

View complete experience →