Score each branch
BMC blocks compare the received pair with each expected pair. The resulting 2-bit Hamming distance becomes the local cost for a candidate transition.
UC San Diego · ECE 111 Final Project · Digital Design
SystemVerilog
Viterbi Decoder
Recovering a bitstream through a noisy channel, one survivor path at a time. An 8-state decoder built around branch metrics, add-compare-select logic, and banked traceback memory.
Implemented a recursive systematic convolutional encoder and modular decoder, then evaluated recovery under periodic, randomized, and burst error injection.
- Implementation
- SystemVerilog RTL
- Code rate / states
- 1/2 · 8 states
- Documented experiments
- 22 error cases
- Periodic cases 2a1–2a5
- 0 output errors
01 / Architecture
From received symbols to recovered bits
The encoder produces two bits per input bit: the original bit and a parity bit derived from the current input and encoder state. The channel wrapper injects errors before the decoder scores candidate paths.
- Received symbol2 channel bits
- BMCHamming distance
- ACS8 survivor decisions
- Survivor memory4 × 1024 × 8 bits
- TracebackRecovered bitstream
Keep the survivor
Eight ACS instances add branch costs to 8-bit path metrics. Validity flags gate candidates; the lower-cost valid path survives. Equal costs select path 0.
Reconstruct the sequence
Four memory banks retain the eight survivor decisions per step. Two traceback units traverse decisions, with display memories staging decoded output.
A concrete ACS decision
Input: both paths valid; prior costs 5, 7; branch costs 2, 1.
Output: path_cost = 7, selection = 0, valid_o = 1.
Why: candidate costs are 5 + 2 = 7 and 7 + 1 = 8, so path 0 survives. This illustrates the combinational rule in ACS.sv.
02 / Design decisions
The integration work behind the datapath
Match encoder and trellis
The final project uses a recursive systematic encoder. Its symbol mapping must match the decoder’s branch metrics; substituting the nonrecursive homework encoder changes that mapping.
Bound the path metrics
The decoder checks the high bit of all eight stored path costs. When all are set, it masks the next ACS costs to seven bits as part of the metric update.
Align memory and traceback
Synchronous memory reads and delayed bank-selection signals coordinate writes, reverse reads, and traceback. Output history is captured after the testbench’s startup delay.
03 / Verification & results
Recovery succeeds—and has a boundary
The end-to-end testbench keeps input and output histories and compares 256 decoded bits after a startup delay. The Part 2 report records 22 experiments spanning periodic errors (2a), randomized errors (2b), and increasingly dense patterns (2c–2e).
| Case | Pattern | Injected errors | Output errors |
|---|---|---|---|
| 2a1 | 01 | 31 | 0 |
| 2a6 | 01010101 | 32 | 30 |
| 2b2 | 10 | 37 | 3 |
| 2c3 | 010101 | 48 | 0 |
| 2c | 01010101 | 64 | 81 |
| 2e | 11111111 | 64 | 44 |
Engineering takeaway: error placement matters alongside error count. These experiments include both complete recovery and patterns that drive the decoder onto an incorrect path. Injected channel-bit errors and decoded output-bit errors are separate measurements.
These are recorded coursework simulation results, not a new benchmark run or a general error-rate guarantee. The published evidence covers RTL and simulation; FPGA utilization, timing closure, and board measurements are not reported here.
04 / Project evidence
Go directly to the implementation
Part 1 · Build
Encoder, BMC, ACS, memories, decoder integration, and simulation captures.
Part 2 · Evaluate
Error-injection variants and recorded outcomes, including failure cases.
Course repository
Final-part-1 and Final-part-2 contain this project. The homework folders are separate exercises.
Put the project in context.
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